The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________ - Study24x7
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Goraksha Dadhich
18 May 2019 10:32 AM study24x7 study24x7

The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________

A

Simulation

B

Synthesis

C

Optimization

D

Verification

Railways IIT-JEE Sciences
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  • geet sharma
    • Synthesis means to generate netlist, i.e. describing the circuit by the relation between inputs and outputs by using logic equations. Simulation is whereas to check the correctness of VHDL code and Optimization is to optimize the netlist; optimization is performed after the synthesis. Verification similarly uses different EDA tool to perform gate level verification.

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    Reply 18 May 2019 12:18 PM
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