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Low Power VLSI Circuits & Systems
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Low Power VLSI Circuits & Systems
by Prof Ajit Pal

VLSI's design tools included not only design entry and simulation but eventually also cell-based routing (chip compiler), a datapath compiler, SRAMand ROM compilers, and a state machine compiler. The tools were an integrated design solution for IC design and not just point tools, or more general purpose system tools. A designer could edit transist...

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FREE
About This Course

VLSI's design tools included not only design entry and simulation but eventually also cell-based routing (chip compiler), a datapath compiler, SRAMand ROM compilers, and a state machine compiler. The tools were an integrated design solution for IC design and not just point tools, or more general purpose system tools. A designer could edit transist...

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Course Curriculum
1 Sections | 40 Lecture | 36h 33min total length
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Low Power VLSI Circuits & Systems

Low Power VLSI Circuits & Systems

| 36h 33min total length
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    Static CMOS Circuits - I

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    MOS Inverters - IV

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    MOS Inverters - III

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    MOS Transistors - IV

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    MOS Transistors - III

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    MOS Inverters - I

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    MOS Inverters - II

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    MOS Transistors - II

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    MOS Transistors - I

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    Introduction & Course Outline

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    Dynamic Power Dissipation

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    Tutorial - I

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    Switching Power Dissipation

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    Finite State Machines

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    MOS Memories

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    Pass Transistor Logic Circuits - II

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    Pass Transistor Logic Circuits - I

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    MOS Dynamic Circuits -II

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    MOS Dynamic Circuits -I

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    Static CMOS Circuits -II

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    Minimizing Switched Capacitance - IV

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    Minimizing Switched Capacitance - III

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    Minimizing Switched Capacitance - II

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    Minimizing Switched Capacitance - I

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    Tutorial - II

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    Supply Voltage Scaling - IV

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    Supply Voltage Scaling - III

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    Supply Voltage Scaling - II

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    Supply Voltage Scaling - I

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    Leakage Power Dissipation

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    Course Summary

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    Tutorial - III

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    CAD Tools for Low Power

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    Battery-Driven System Design

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    Adiabatic Logic Circuits

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    Variation Tolerant Design

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    Minimizing Leakage Power - III

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    Minimizing Leakage Power - II

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    Minimizing Leakage Power - I

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    Minimizing Switched Capacitance - V

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