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Design Verification and Test of Digital VLSI Circuits
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Design Verification and Test of Digital VLSI Circuits
by Dr Santosh Biswas

Design for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no manufacturin...

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About This Course

Design for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no manufacturin...

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Course Curriculum
11 Sections | 43 Lecture | 44h 26min total length
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Design Verification and Test of Digital VLSI Circuits

Introduction

| 03h 06min total length
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    Introduction to Digital VLSI Design Flow

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    High Level Design Representation

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    Transformations for High Level Synthesis

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Design Verification and Test of Digital VLSI Circuits

Scheduling , Allocation and Binding

| 04h 12min total length
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    Scheduling Algorithms-1

    57m <?php echo $alt; ?>
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    Introduction to HLS: Scheduling, Allocation and Binding Problem

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    Scheduling Algorithms-2

    1h 70 min <?php echo $alt; ?>
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    Binding and Allocation Algorithms

    1h 67 min <?php echo $alt; ?>
Design Verification and Test of Digital VLSI Circuits

Logic Optimization and Synthesis

| 06h 23min total length
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    Two level Boolean Logic Synthesis-1

    1h 63 min <?php echo $alt; ?>
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    Two level Boolean Logic Synthesis-2

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    Two level Boolean Logic Synthesis-3

    1h 63 min <?php echo $alt; ?>
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    Heuristic Minimization of Two-Level Circuits

    1h 63 min <?php echo $alt; ?>
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    Finite State Machine Synthesis

    1h 63 min <?php echo $alt; ?>
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    Multilevel Implementation

    1h 63 min <?php echo $alt; ?>
Design Verification and Test of Digital VLSI Circuits

Temporal Logic

| 04h 10min total length
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    Equivalence between CTL Formulas

    1h 68 min <?php echo $alt; ?>
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    Temporal Logic: Introduction and Basic Operators

    1h 60 min <?php echo $alt; ?>
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    Syntax and Semantics of CTL

    1h 60 min <?php echo $alt; ?>
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    Introduction to formal methods for design verification

    1h 60 min <?php echo $alt; ?>
Design Verification and Test of Digital VLSI Circuits

Verification Techniques

| 03h 49min total length
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    Model Checking with Fairness

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    Model Checking Algorithms II

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    Introduction to Model Checking

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    Model Checking Algorithms I

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Design Verification and Test of Digital VLSI Circuits

Binary Decision Diagram

| 05h 09min total length
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    Symbolic Model Checking

    1h 61 min <?php echo $alt; ?>
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    Ordered Binary Decision Diagram for State Transition Systems

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    Operation on Ordered Binary Decision Diagram

    1h 61 min <?php echo $alt; ?>
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    Ordered Binary Decision Diagram

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    Binary Decision Diagram: Introduction and construction

    1h 61 min <?php echo $alt; ?>
Design Verification and Test of Digital VLSI Circuits

Introduction to Digital Testing

| 02h 51min total length
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    Fault Equivalence

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    Functional and Structural Testing

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    Introduction to Digital VLSI Testing

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Design Verification and Test of Digital VLSI Circuits

Fault Simulation and Testability Measures

| 03h 59min total length
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    Fault Simulation-1

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    Fault Simulation-2

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    Fault Simulation-3

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    Testability Measures (SCOAP)

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Design Verification and Test of Digital VLSI Circuits

Combinational Circuit Test Pattern Generation

| 03h 16min total length
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    D-Algorithm-2

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    D-Algorithm-1

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    Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras

    1h 65 min <?php echo $alt; ?>
Design Verification and Test of Digital VLSI Circuits

Sequential Circuit Testing and Scan Chains

| 02h 36min total length
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    Scan Chain based Sequential Circuit Testing-2

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    Scan Chain based Sequential Circuit Testing-1

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    ATPG for Synchronous Sequential Circuits

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Design Verification and Test of Digital VLSI Circuits

Built in Self test (BIST)

| 04h 50min total length
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    Memory Testing-2

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    Memory Testing-1

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    Built in Self Test-2

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    Built in Self Test-1

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show 8 more sections