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Advanced VLSI Design

by Prof. A.N. Chandorkar

Historical Perspective of VLSI, CMOS VLSI Design for Power and Speed consideration, Logical Efforts: Designing Fast CMOS Circuits; Datapath Design, Interconnect aware design, Hardware Description Languages for VLSI Design, FSM Controller/Datapath and Processor Design, VLSI Design Automation, and VLSI Design Test and Verification....

5.0 (865 Ratings) 1445 Learner

Validity Unlimited

All Level

English

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Program Fee

FREE

About This Course

Course Curriculum

1 Sections | 42 Lecture | 44h 06min total length

Expand all sections

Advanced VLSI Design

| 44h 06min total length

L1-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design
53m
L2-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design - Part II
1h 102 min
L3-Logical Effort - A way of Designing Fast CMOS Circuits
1h 66 min
L4-Logical Effort - A way of Designing Fast CMOS Circuits continued?
1h 72 min
L5-Logical Effort - A way of Designing Fast CMOS Circuits -Part III
1h 75 min
L6-Power Estimation and Control in CMOS VLSI circuits
1h 60 min
L7-Power Estimation and Control in CMOS VLSI circuits continued
1h 79 min
L8-Low Power Design Techniques
54m
L9-Low Power Design Techniques -Part II
1h 111 min
L10-Arithmetic Implementation Strategies for VLSI
57m
L11-Arithmetic Implementation Strategies for VLSI -Part II
59m
L12-Arithmetic Implementation Strategies for VLSI -Part III
1h 109 min
L13-Arithmetic Implementation Strategies for VLSI -Part IV
1h 95 min
L14-Interconnect aware design: Impact of scaling, buffer insertion and inductive peaking
53m
L15-Interconnect aware design: Low swing and Current mode signaling
53m
L16-Interconnect aware design: capacitively coupled interconnects
49m
L17-Introduction to Hardware Description Languages
51m
L18-Managing concurrency and time in Hardware Description Languages
53m
L19-Introduction to VHDL
52m
L20-Basic Components in VHDL
51m
L21-Structural Description in VHDL
52m
L22-Behavioral Description in VHDL
51m
L23-Introduction to Verilog
51m
L24-FSM datapath (GCD example)
58m
L25-FSM datapath (continued)
54m
L26-Single Cycle MMIPS
54m
L27-Multicycle MMIPS
1h 76 min
L28-Multicycle MMIPS? FSM
1h 81 min
L29-Brief Overview of Basic VLSI Design Automation Concepts
1h 61 min
L30-Netlist and System Partitioning
1h 62 min
L31-Timing Analysis in the context of Physical Design Automation
1h 65 min
L32-Placement algorithm
48m
L33-Introduction to VLSI Testing
56m
L34-VLSI Test Basics - I
59m
L35-VLSI Test Basics - II
58m
L36-VLSI Testing: Automatic Test Pattern Generation
55m
L37-VLSI Testing: Design for Test (DFT)
56m
L38-VLSI Testing: Built-In Self-Test (BIST)
58m
L39-VLSI Design Verification: An Introduction
54m
L40-VLSI Design Verification: An Introduction
52m
L41-VLSI Design Verification: Equivalence/Model Checking
50m
L42-VLSI Design Verification: Model Checking
1h 60 min